The present invention is related to signal processing and, specifically, to signal measurement devices used in automatic test equipments.
Time-to-digital converters (TDC) in automatic test equipment applications time stamp selected events from the device under test (DUT), i.e. measure the arrival time relative to a tester clock. A time stamper is also known as a continuous time interval analyzer.
Time stamp measurements have a large number of applications in test, each with different requirements. Jitter measurements of high-speed serial interfaces necessitate a high resolution of about 1% of a bit period, i.e. 3 ps at 3 Gbps and can be made using time stamps. The signal may have an arbitrary phase relative to the tester clock. Skew measurements between clock and data of source-synchronous busses necessitate a high resolution of about 1% of bit period combined with a highest possible sample rate to obtain high coverage of sporadic timing violations. Clock-to-output measurements of slow digital outputs necessitate a very large dynamic range at moderate resolution. I/Q phase imbalance measurements can necessitate 1 ps resolution in a dynamic range of 1 μs. Dynamic PLL measurements necessitate sample rates in the order of 100 Msa/s (mega samples per second) to follow the loop dynamics. Write-precompensation tests of DVD and HDD channels necessitate fast and accurate time measurements.
A fully digital time-to-digital converter is disclosed in “Fully Digital Time-to-Digital Converter for ATE with Autonomous Calibration”, Jochen Rivoir, International Test Conference 2006, paper 6.3.
A vernier delay line is described, which is a fast “flash” version of a vernier oscillator TDC, which is also known as a component-invariant delay line. In a vernier delay line, two delay line branches with slightly different average gate delays achieve an average sub-gate delay resolution. The measured event injects a pulse into this slow delay line with average buffer delays, the next coarse clock edge is injected into the fast delay line with different average buffer delays. Starting with an initial time difference, each stage reduces the difference by a nominal delta value until the time difference becomes negative after a number of c stages. Flip-flops in each stage act as phase arbiters between the two racing pulses. A positive phase difference is captured as “1” and a negative phase difference is captured as a logical “0”, where the negative phase difference happens in a stage c at a first time. A priority encoder is connected to the output of each phase arbiter and the priority encoder outputs the first stage capturing a “0” value. Vernier delay differences of between the delays in one stage of about 1 ps are possible with modern CMOS processes. A fine time range TR which equals one coarse clock period necessitates
  S  =            T      R              Δ      ⁢                          ⁢      τ      stages. When using a parallel read-out, the propagation time through S buffers with a delay τs limits the sample rate to
      F    S    =            1              S        ⁢                                  ⁢                  τ          s                      =          Δτ                        T          R                ⁢                  τ          s                    
However, unavoidable gate delay mismatches lead to non-linearities and even significantly non-monotonic behavior. To address this issue, a statistical linearity calibration is implemented, which uses a large number of events that are uniformly distributed across one coarse clock period, i.e. the time range of the vernier delay line interpolator. On average, the number of captured “1” in a given vernier stage is proportional to its accumulated vernier delay and, thus, can be used to calibrate the vernier delay line (VDL). A (free running) ring oscillator can generate events that are uncorrelated to the coarse clock to a sufficient degree and, thus, uniformly distributed.
In high-resolution designs, the chain of accumulated vervier delays can easily be non-monotonic. This means that from one stage to the next, the accumulated venier delay can remain the same or can even decrease. On average, an accumulated venier delay increases, for example, by 1 ps per stage, but varies from −3 ps to +5 ps between subsequent stages. For non-monotonic accumulated venier delays Tk, there can be multiple stage changes between neighboring flip-flops. Finding the stage with the closest accumulated venier delay using real-time hardware necessitates knowing all accumulated delays. Therefore, typical flash convertees, such as the venier delay line TDC uses a simple priority encoder to identify the stage number c of the first flip-flop that captures a “0”. Thus, stages whose Tk is smaller than those of previous stages are ignored.
The statistical linearity calibration is based on a code density calibration. Specifically, a probability pc of hitting code c is proportional to the time window that leads to code c, i.e. the increase of Gc from the previous stage c-1. For N events, code c can be expected, {circumflex over (n)}c times
            n      ^        c    =            Np      c        =          N      ⁢                          ⁢                        D          c                          T          R                    
The actual count nc can be used for an estimate {tilde over (D)}c of the monotonic increase Dc
            D      ~        c    =                    n        c            N        ⁢          T      R      
IteratingDc=Gc−Gc-1 yields the estimated accumulated vernier delays {tilde over (G)}c
            G      ~        c    =                              G          ~                          c          -          1                    +                        D          ~                c              =                  ∑                  i          =          1                c            ⁢                        D          ~                i            
A mission-mode measurement with code c will return the calibrated measured time interval {tilde over (t)} as the mean of the two adjacent growing delays.
      t    ~    =                    1        2            ⁢              (                                            G              ~                        c                    +                                    G              ~                                      c              -              1                                      )              =                            ∑                      i            =            1                                c            -            1                          ⁢                              D            ~                    i                    +                        1          2                ⁢                              D            ~                    c                    
While this concept is advantageous for several applications due to the easy-to-implement and fast-to-implement calibration process, nevertheless, there exists a situation in which the accuracy of the measurements is not fully optimum.